The present disclosure relates to branch prediction in computer processors, and more specifically, to specific uses of history data in branch prediction.
Many computer processor circuits use instruction pipelines to increase the number of instructions that can be executed in a unit of time. The execution of a single instruction can be separated in to a series of divisible operations that form a pipeline. Accordingly, multiple instructions can be in various stages of execution at the same time. When a conditional branch instruction is encountered, the computer processor may not be able to know for certain what instructions will be executed next because the condition for branching may not be known at the time the branch instruction is loaded into the pipeline. Branch prediction techniques can be used to guess whether or not the conditional branch will be taken, before it is known for certain. Good branch prediction can reduce the delays that are caused by having to back out partially executed instructions loaded due to an incorrect branch prediction.